Characteristics of a successive approximation analog/digital converter (A/D converter) are that circuit configuration is relatively simple, compatibility with CMOS processing is high, manufacturing cost is relatively low, and conversion time can be relatively short. Due to this, a successive approximation A/D converter is used in various applications. In concrete terms, a successive approximation A/D converter is used as an A/D conversion circuit which is built in to a microcontroller (MCU).
A successive approximation A/D converter has a sampling circuit which samples analog voltage, a digital/analog converter (DAC) which generates internal analog voltage, a comparator which compares sampling voltage and internal analog voltage, and a control circuit having a successive approximation register for storing a comparison result of the comparator. In other words, the successive approximation A/D converter samples analog voltage, operates an input digital code of the DAC so that the sampled voltage and the output voltage of the internal DAC become the closest, and outputs a final DAC input code as the digital signal. In the successive approximation, binary search is performed, where operation to generate intermediate reference voltage in a block including analog voltage by the internal DAC is repeated.
The successive approximation A/D converter has a main DAC and a sub-DAC, in order to decrease a size of a capacitive element (capacitor) of the DAC. For example, in the case of A/D conversion of M+N bits, the significant M bits are determined by the main DAC, and the insignificant N bits are determined by the sub-DAC. Such a successive approximation A/D converter is written in patent documents like, Japanese Patent Application Laid-Open No. 2004-32089, No. 2004-80075, No. 2004-200926, No. 2005-86550, No. 2007-49637, No. 2007-142863 and U.S. Pat. Nos. 6,714,151, 6,867,723, 7,199,745, and 7,233,273.
The successive approximation A/D converter also has a correction DAC or a correction capacitive element (adjustment capacitive element) for correcting the manufacturing dispersion of the capacitance element (capacitor) of the DAC. Using the correction DAC and the adjustment capacitive element, conversion errors due to the manufacturing dispersion of the capacitive element of the DAC are suppressed. Such a self-correcting successive approximation A/D converter is disclosed in patent documents like, Japanese Patent Application Laid-Open No. S59-83418, No. S59-133728, U.S. Pat. No. 6,985,101, Japanese Patent Application Laid-Open No. 2009-232281, and non-patent documents like, Toshiro Tsukada, Katsuaki Takagi, Yuzo Kida, Minoru Nagata “Self-calibrating high precision MOS, A/D Converter”, IEICE Transactions (C) Vol. 66, No. 11, 1983; T. Tsukada, K. Takagi, Y. Kita, M. Nagata, “An automatic error cancellation techniqure for higher accuracy A/D converters”, IEEE J. Solid-State Circuits, vol. SC-19, No. 2, 1984; H. S. Lee, D. A. Hodges, “Self-Calibration technique for A/D converters”, IEEE Transactions on Circuits and Systems, Vol. CAS-30, No. 3, March, 1983; H. S. Lee, D. A. Hodges, “A Self-Calibrating 15 Bit CMOS A/D Converter”, IEEE Journal of Solid-State Circuits Vold SC-19, No. 6, December 1984; H. S. Lee, D. A. Hodges,“Accuracy Considerations in Self-Calibrating A/D Converters”,IEEE Transactions on Circuits and Systems Vol. 2 CA S-32, No. 6, June 1985; Ka Y. Leung, Kafai Leung, Douglas R. Holberg, “A Dual Low Power 1/2LSB INL 16b/1Msample/s SAR A/D Converter with on-chip Microcontroller”, Asian Solid-State Circuits Conference, Digest of Technical papers, 2006.
A self correcting successive approximation A/D converter detects error voltage between two states where the correction target capacity elements are balanced in the top node of the main DAC, which is an input of a comparator, and a correction code is determined corresponding to the error voltage. Then according to the correction code, the output voltage of the correction DAC is corrected or the capacitance of the adjustment capacitive element is adjusted according to the correction code.
An error occurs between these two states because of the offset voltage due to the ON/OFF operation of a switch element disposed in the comparator, and the offset voltage of the comparator voltage. The offset voltage causes a drop in correction accuracy.